Diminished-One Modulo (2 + 1) Multiplier Design

A technique, based on the residue number system (RNS) with operands in the diminished-1 number system, has been used in several applications which include digital signal processing (DSP), implementation international data encryption algorithm (IDEA), Fermat number transform (FNT), and so on. For implementation of these techniques, several designs for modulo 2+1 diminished-1 arithmetic blocks have been proposed. Modulo (2 + 1) diminished-1 multiplication plays an important role in these arithmetic blocks. Existing algorithms for modulo (2 + 1) diminished-1 multiplication use either recursive modulo (2 + 1) addition, or regular binary multiplication integrated with the modulo reduction operation. This paper proposes an enhanced approach for the design modulo 2 + 1 multipliers for diminished-1 operands with respect to those which have been already published. It is improved in a way that the proposed memoryless based multiplication can be decomposed into a number of small units. The architecture for the new multipliers consists of new partial product generator, inverted end-around-carry, carry-save-adder tree and one (2+ 1) adder.